1. Field of Invention
The present invention relates to a method of fabricating a metal-oxide-semiconductor (MOS) transistor. More particularly, the present invention relates to a method of fabricating a MOS transistor capable of increasing pad area size as well as improving alignment accuracy in subsequent processes.
2. Description of Related Art
A MOS transistor is a basic device in an integrated circuit. A MOS transistor unit comprises a gate structure, a source region and a drain region, wherein the gate structure includes a metallic layer and an oxide layer. In general, the metallic layer is made from a material having properties very close to silicon such as polysilicon, and the oxide layer is made from silicon dioxide (SiO.sub.2). The source/drain regions are formed in a substrate on either side of the gate structure.
Conventionally, the metallic layer is a composite layer made from a doped polysilicon layer and a tungsten silicide layer. Polysilicon is used because it adheres well to the oxide layer. However, to increase a transistor device's data transmission speed, it is customary to deposit a highly conductive layer over the doped polysilicon layer. In addition, a highly conductive layer is also deposited on the surface above the source/drain regions. Preferably, the highly conductive layer is a tungsten silicide layer. Nevertheless, as devices are miniaturized, correctly aligning the layer of conductive material to the designated device region becomes more difficult. Furthermore, the deposition of a conductive layer over a polysilicon layer has to be carried out separately from the deposition of a conductive layer over the source/drain regions.
FIGS. 1A through 1F are cross-sectional views showing the progression of manufacturing steps taken to fabricate a MOS transistor according to a conventional method.
First, as shown in FIG. 1A, a semiconductor substrate 10 is provided. Next, a photoresist layer and a photomask are used to define devices' active areas. Thereafter, devices are isolated from each other by forming device isolation structures. For example, shallow trench isolation (STI) structures 12 are formed.
Next, as shown in FIG. 1B, a silicon dioxide layer having a thickness of about 100-250 .ANG. is formed over the entire substrate 10 using, for example, a thermal oxidation method. The silicon dioxide layer functions as a gate oxide layer 14 for the MOS transistor. Thereafter, a polysilicon layer 16 having a thickness of about 2000-3000 .ANG. is deposited over the gate oxide layer 14 using, for example, a low-pressure chemical vapor deposition (LPCVD) method. Subsequently, highly concentrated phosphorus or arsenic ions are doped into the polysilicon layer 16 using either a heat diffusion method or an ion implantation method. Consequently, resistivity of the polysilicon layer 16 is greatly lowered. Later, a photoresist layer 20 is formed over the polysilicon layer 16 and then patterned to form a mask for defining the gate structure.
Next, as shown in FIG. 1C, the doped polysilicon layer 16 and the gate oxide layer 14 are etched to form a polysilicon layer 16a and gate oxide layer 14a by using the photoresist layer 20 as a mask. Together, the polysilicon layer 16a and the gate oxide layer 14a form the gate structure of the MOS transistor. Thereafter, the photoresist layer 20 is removed using, for example, sulfuric acid (H.sub.2 SO.sub.4).
Next, as shown in FIG. 1D, using the polysilicon layer 16a as a mask, the substrate 10 is doped to form lightly doped source/drain regions by implanting phosphorus ions, for example. Concentration level of the implanted ions is about 10.sup.13 /cm.sup.2, which is low.
Next, as shown in FIG. 1E, a dielectric layer is formed over the entire substrate structure. The dielectric layer is, for example, a silicon dioxide layer, a silicon nitride layer or other layers having properties similar to the two above. Thereafter, a portion of the dielectric layer is removed to expose a large portion of the source/drain region, and forming spacers 24 on the sidewalls of the polysilicon layer 16a and gate oxide layer 14a. The dielectric layer is removed by, for example, an anisotropic dry etching method. In the subsequent step, using the polysilicon layer 16a and the spacers 24 as masks, the substrate 10 is doped to form heavily doped source/drain regions 18a by implanting phosphorus or arsenic ions, for example. Concentration level of this second implant is higher than the first light implantation, roughly about 10.sup.15 /cm.sup.2, and implantation depth is also much deeper.
Next, as shown in FIG. 1F, a dielectric layer 26 is formed over the entire substrate structure. The dielectric layer is made from silicon dioxide, for example. Then, the dielectric layer 26 is patterned to form an opening 30 that exposes a portion of the polysilicon layer 16a. Thereafter, a conductive layer 32 such as tungsten is deposited over the dielectric layer 26 and completely fills the opening 30 so that electrical connection with the polysilicon layer 16a is achieved. Subsequently, the conductive layer 32 is patterned to form local interconnect or a pad.
Finally, subsequent processing operations are carried out to complete the fabrication of the MOS transistor. Since these processes are not directly related to this invention, details are omitted here.
However, as the level of integration continue to increase, dimensions of a semiconductor device shrink correspondingly. Therefore, when the conductive layer is formed, it is difficult to correctly align the conductive layer to the target region. In the process of patterning the dielectric layer 26, if there is a shift in the location of the opening 30, subsequently deposited conductive layer 32 will be out of alignment with the opening 30. Therefore, the required electrical connection between the conductive layer 32 and the polysilicon layer 16a will not established, which leads to circuit failure.
In light of the foregoing, there is a need to provide a better method of fabricating a MOS transistor.